An organic light emitting diode display has advantages of high response speed, light weight, flexible and wide viewing angle with respect to a liquid crystal display. An active matrix organic light emitting diode (AMOLED) has advantages of low driving current and low power consumption, and is suitable for high-resolution display. The architecture of the active matrix organic light emitting diode may be driven by using amorphous silicon, polysilicon, oxide semiconductor or organic thin film transistor, since a carrier mobility and a driving current of amorphous silicon or organic thin film transistor are small, a voltage required for driving high-luminance organic light emitting diode is high and a generated device size is large. However, the low-temperature polysilicon has the mobility up to 100 cm2/V·s, the high current characteristic of the low-temperature polysilicon meets stringent requirement for the organic light emitting diode, and the driving scheme with low operating voltage and high density facilitates longer lifetime of the organic light emitting diode. Different from a voltage driving scheme of conventional liquid crystal display, the driving for the organic light emitting diode requires a special current driving scheme, and two to six thin film transistors are generally required to be provided in a same pixel so as to achieve a compensation circuit involving uniformities of grayscale and panel. High-density layout characteristic of the low-temperature polysilicon thin film transistors facilitates implementation of the organic light emitting diode panel with high luminance and high definition. Currently, most of the AMOLED displays through successful commercial production utilize the array substrate having the low-temperature polysilicon.
In the process of fabricating conventional low-temperature polysilicon array substrate, eight to nine exposing processes are generally required. The process of fabricating the low-temperature polysilicon array substrate shown in FIG. 1 in the prior art will be described below.
A buffer layer 2 of silicon dioxide (SiO2) and silicon nitride (SiN) films is formed on entire substrate 1 by plasma enhanced chemical vapor deposition (PECVD). Then, amorphous silicon (a-Si) film is formed on the buffer layer 2 by PECVD or other chemical (or physical) vapor deposition. The a-Si film is crystallized into polysilicon film by laser annealing (ELA) or solid phase crystallization (SPC). A polysilicon active layer 3 is then formed by using conventional exposing and etching processes. Low-concentration ion doping is performed by using ion implantation process, so as to form a semiconductor active region required by the thin film transistor in the polysilicon active layer 3.
A gate insulation layer 4 is formed by depositing SiO2 film or SiO2 and SiN films by PECVD on the substrate 1 on which the active layer 3 is formed. One or more metal material films with low resistance are deposited on the gate insulation layer 4 by physical vapor deposition such as magnetron sputtering, and a gate 5 is formed by photolithography process.
A passivation layer 6 and via holes for connecting a source 7 and a drain 8 with the active layer 3 are formed on the substrate 1 on which the gate 5 is formed, by depositing SiO2 and SiN films by PECVD, and by exposing and etching processes.
One or more metal films with low resistance are deposited by magnetron sputtering, and the source 7 and the drain 8 are formed by exposing and etching processes, the source 7 and the drain 8 are in ohmic contact with the polysilicon active layer 3 through the corresponding via holes, respectively.
A planarization layer 9 is formed by PECVD on the substrate 1 subjected to above steps, and via holes are formed by patterning process.
A layer of transparent conductive film is formed by magnetron sputtering on the substrate 1 subjected to above steps, and a pixel electrode 10 of pixel region is formed by photolithography process.
A pattern comprising a pixel defining layer 11 is formed by patterning process on the substrate 1 subjected to above steps.
As can be seen from above, at least six to seven photolithography processes are required to form the structure of the low-temperature polysilicon array substrate shown in FIG. 1, resulting in long process time and low process yield, so that fabrication cost of the array substrate is high. Further, the inventor finds that, since excess silicon atoms migrate to portions between the grains during crystallization, the polysilicon film has convex portions at grain boundary regions, resulting in high-roughness upper surface of the polysilicon film and rough interface between the polysilicon active layer 3 and the gate insulation layer 4, so that performance of the thin film transistor is degraded and process failure is produced.